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Chrontel
CH7303
Preliminary Advanced Information
Chrontel CH7303 HDTV / DVI Encoder
Features
* Digital Visual Interface (DVI) Transmitter up to 165M pixels/second * DVI low jitter PLL * DVI hot plug detection * Analog YPrPb outputs for HDTV * HDTV support for 480p, 576p, 720p, 1080i and 1080p * MacrovisionTM copy protection support for HDTV * Programmable digital input interface supporting RGB (15, 16, 24 or 30 bit) and YCrCb input data formats * Can output either RGB or YPrPb * TV / Monitor connection detect * Programmable power management * Three 10-bit video DAC outputs * Fully programmable through serial port * Complete Windows and DOS driver support * Low voltage interface support to graphics device * Offered in a 64-pin LQFP package * Backward pin compatible with CH7301 or CH7009/11 * Support three additional 15 bit multiplexed RGB Input Data Format (IDF 6,7.8)
Patent number 5,781,241 Patent number 5,914,753
General Description
The CH7303 is a Display Controller device which accepts a digital graphics input signal, and encodes and transmits data through a DVI link (DFP can also be supported), VGA ports (analog RGB) or a HDTV port (YPrPb). The device is able to encode the video signals and generate synchronization signals for analog HDTV interface standards and graphics standards up to UXGA. The device accepts data over one 15-bit wide variable voltage data port which supports 9 different data formats including RGB and YCrCb. The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all circuitry required to encode, serialize and transmit data. The CH7303 is able to drive a DFP display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device. In addition to DVI encoder modes, bypass modes are included which perform color space conversion to HDTV standards and generate and insert HDTV sync signals, or output VGA style analog RGB for use as a CRT DAC.
Note: Other names and brands may be claimed as property by others.
HPDET GPIO[1:0] AS SPC SPD RESET* H,V DE VREF
2
Serial Port Control
/ 24
DVI PLL DVI Encode DVI Serialize DVI Driver
/ 2 / 2 / 2 / 2 / 2
TLC, TLC* TDC0, TDC0* TDC1, TDC1* TDC2, TDC2* HSYNC, VSYNC
H,V,DE Latch
/ 2
XCLK,XCLK*
2
Clock Driver
/ 24
Color Space Conversion Sync Decode
HDTV
YPbPr
DAC 2 DAC 1 DAC 0
DAC[2] DAC[1] DAC[0]
D[14:0] ISET
15
Data Latch, Demux
MUX
RGB
/ 30
/ 30
Three 10-bit DAC's
Figure 1: Functional Block Diagram 209-0000-031 Rev. 0.4, 8/26/2002 1
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1.0 Pin-Out
1.1 Package Diagram
CH7303
XCLK*
DGND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVDD DE VREF H V DGND GPIO[1] / HPINT GPIO[0] HPDET AS DGND DVDD RESET* SPD SPC AGND
DVDD
XCLK
D[10]
D[11]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Chrontel CH7303
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
H SYNC V SYNC D[12] VDDV AVDD D[13] D[14] AGND GND B/Pb R/Pr G/Y N/C ISET GND VDD
AGND
AVDD
TDC0*
TDC1*
TDC2*
TDC0
TDC1
TVDD
TDC2
TVDD
TGND
TGND
TLC*
TLC
VSWING
Figure 2: 64-Pin LQFP Package
2
209-0000-031
TGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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1.2 Pin Description
# Pins 1 In Type Symbol DE Description Data Enable
CH7303
Table 1: Pin Description Pin # 2
This pin accepts a data enable signal which is high when active video data is input to the device, and low all other times. The levels are 0 to VDDV, and the VREF signal is used as the threshold level. This input is used by the DVI.
3
1
In
VREF
Reference Voltage Input
The VREF pin inputs a reference voltage of VDDV / 2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync, data enable and clock inputs.
4
1
In
H
Horizontal Sync Input
This pin accepts a horizontal sync input for use with the input data. The amplitude will be 0 to VDDV and the VREF signal is used as the threshold level.
5
1
In
V
Vertical Sync Input
This pin accepts a vertical sync input for use with the input data. The amplitude will be 0 to VDDV and the VREF signal is used as the threshold level.
7
2
In/Out
GPIO[1] / HPINT
DVI Link Detect Output
When the GPIO[1] pin is configured as an output, this pin can be used to output the DVI detect signal (pulls low when a termination change has been detected on the HPDET input). This is an open drain output. The output is released through serial port control.
8
2
In/Out
GPIO[0]
General Purpose Input - Output[0] (Weak internal pull-up)
This pin provides a general purpose I/O controlled via the serial port. The internal pull-up will be to the DVDD supply.
9
1
In
HPDET
Hot Plug Detect (internal pull-down)
This input pin determines whether the DVI is connected to a DVI monitor. When terminated, the monitor is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via GPIO[1]/TLDET* pin pulling low.
10 13 14
1 1 1
In In In/Out
AS RESET* SPD
Address Select (Internal pull-up)
This pin determines the serial port address of the device (1,1,1,0,1,AS*,AS).
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port register.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and operates with inputs from 0 to VDDV. Outputs are driven from 0 to VDDV.
15 19
1 1
In In
SPC VSWING
Serial Port Clock Input
This pin functions as the clock input of the serial port and operates with inputs from 0 to VDDV.
DVI Swing Control
This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor should be connected between this pin and TGND using short and wide traces.
22, 21 25, 24
2 2
Out Out
TDC0, TDC0* TDC1, TDC1*
DVI Data Channel 0 Outputs
These pins provide the DVI differential outputs for data channel 0 (blue).
DVI Data Channel 1 Outputs These pins provide the DVI differential outputs for data channel 1 (green).
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Table 1: Pin Description (contd.) Pin # 28, 27 30, 31 35 # Pins 2 2 1 Type Out Out In Symbol TDC2, TDC2* TLC, TLC* ISET Description DVI Data Channel 2 Outputs
CH7303
These pins provide the DVI differential outputs for data channel 2 (red).
DVI Clock Outputs
These pins provide the differential clock output for the DVI interface corresponding to data on the TDC[0:2] outputs.
Current Set Resistor Input
This pin sets the DAC current. A 140 ohm resistor should be connected between this pin and DAC ground (pins 34 and 40) using short and wide traces.
37
1
Out
Y/G
(DAC1)
Luma / Green Output
This pin outputs a selectable video signal. The output is designed to drive a 75ohm doubly terminated load. The output can be selected to be the luminance component of YprPb or Green.
38
1
Out
R/Pr
(DAC2)
Red / Pr Output
This pin outputs a selectable video signal. The output is designed to drive a 75ohm doubly terminated load. The output can be selected to be the Pr component of YPrPb or red.
39
1
Out
B/Pb
(DAC0)
Blue / Pb Output
This pin outputs a selectable video signal. The output is designed to drive a 75ohm doubly terminated load. The output can be selected to be the Pb component of YPrPb or blue.
47
1
Out
VSYNC
VSYNC By programming BCO register, a buffered version of VGA vertical sync
can be acquired from this pin . This output pin can also provide a buffered clock output, driven by the DVDD supply.
48
1
Out In/Out
HSYNC
Horizontal Sync Output
A buffered version of VGA horizontal sync can be acquired from this pin via DC register)
50 -55, 15 58 -63, 42, 43, 46 57, 56 2
D[14] - D[0] Data[14] through Data[0] Inputs
These pins accept the 15 data inputs from a digital video port of a graphics controller. The levels are 0 to VDDV, and the VREF signal is used as the threshold level.
In
XCLK, XCLK*
External Clock Inputs
These inputs form a differential clock signal input to the CH7303 for use with the H, V, DE and D[14:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The clock polarity used can be selected using the MCP control bit.
1, 12, 49 6, 11, 64 45 23, 29 20, 26, 32 18, 44 16, 17, 41 33 34, 40
3 3 1 2 3 2 3 1 2
Power Power Power Power Power Power Power Power Power
DVDD DGND VDDV TVDD TGND AVDD AGND VDD GND
Digital Supply Voltage (3.3V) Digital Ground I/O Supply Voltage (1.1V to 3.3V) DVI Transmitter Supply Voltage (3.3V) DVI Transmitter Ground PLL Supply Voltage (3.3V) PLL Ground DAC Supply Voltage (3.3V) DAC Ground
4
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2.0 Functional Description
2.1 TV Output Operation
CH7303
The CH7303 is capable of being operated as in one of several bypass modes for driving monitors requiring component video signals (HDTV, multi-sync monitors, etc.). All modes make use of the same set of DAC's, and therefore cannot be used simultaneously. Table 2 describes the possible operating modes. A `p' following a number in the Input Scan Type column indicates a progressive scan (non-interlaced) input where the number indicates the active number of lines per frame. An `i' following a number in the Input Scan Type column indicates an interlaced input where the number indicates the active number of lines per frame. Detailed descriptions of each of the operating modes follows Table 2. Table 2: Operating Modes Input Scan Input Data Type Format non-interlaced RGB non-interlaced (480p, 576p, 720p) Interlaced (1080i) non-interlaced (1080p) RGB / YCrCb1 RGB / YCrCb1 RGB / YCrCb1 Output scan Type non-interlaced non-interlaced interlaced non-interlaced Output Format RGB YpbPr2,3 YpbPr3 YpbPr3 Operating Mode RGB bypass HDTV/EDTV bypass HDTV/EDTV bypass (1080i) HDTV/EDTV bypass (1080p)
2.1.1 HDTV / EDTV Bypass In HDTV / EDTV Bypass mode, data, sync and clock signals are input to the CH7303 from a graphics device in the scanning method that matches the display device (interlaced data is sent to the CH7303 to drive an interlaced display, non-interlaced data is sent to the CH7303 to drive a non-interlaced display). The input data format can be YCrCb or RGB. Horizontal and vertical sync signals must either be sent to the CH7303 from the graphics device or embedded in the data stream according to SMPTE standards. Data is 2X multiplexed, and the XCLK clock signal can be 1X or 2X times the pixel rate. Input data is color space converted to the selected video format, has sync signals generated and is output from the video DAC's. The output format is YPbPr. The graphics resolutions supported for HDTV Bypass mode are shown in Table 3 below. The resolutions supported for EDTV Bypass mode are shown in Table 3 below. Table 3: HDTV Bypass Active Total Resolution Resolution 1280x720 1650x750 1280x720 1920x1080 1920x1080 1920x1080 1920x1080 1648x750 2200x1125 2640x1125 2376x1250 2200x1125 Scan Type Non-Interlaced Non-Interlaced Interlaced Interlaced Interlaced Non-Interlaced Pixel Clock (MHz) 74.25 74.25/1.001 74.160 74.25 74.25/1.001 74.25 74.25 148.5 148.5/1.001 74.25 74.25/1.001 148.5 74.25 74.25 74.25/1.001 74.304 148.5 Frame Rate (Hz) 60 60/1.001 60 30 30/1.001 25 25 60 60/1.001 30 30/1.001 50 25 24 24/1.001 24 50 Standard SMPTE 296M SMPTE 274M SMPTE 274M SMPTE 295M SMPTE 274M
1920x1080 1920x1080 1920x1080 1920x1080
2640x1125 2750x1125 2752x1125 2376x1250
Non-Interlaced Non-Interlaced Non-Interlaced Non-Interlaced
SMPTE 274M SMPTE 274M SMPTE 295M
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Table 4: EDTV Bypass Active Total Resolution Resolution 720x480 858x525 720x483 858x525 720x480 856x525 720x483 856x525 720x576 864x625 Scan Type Non-Interlaced Non-Interlaced Non-Interlaced Non-Interlaced Non-interlaced Pixel Clock (MHz) 27.0 27.027 26.937 26.964 27.0 Frame Rate (Hz) 60/1.001 60 60/1.001 60 50 Standard EIA-770.2-A SMPTE 293M ITU-R BT.1358
CH7303
2.1.2 RGB Bypass In RGB Bypass mode, data, sync and clock signals are input to the CH7303 from a graphics device, and bypassed directly to the D/A converters to implement a second CRT DAC function. External sync signals must be supplied from the graphics device. These sync signals are buffered internally, and can be output to drive the CRT. The input data format must be RGB in this operating mode. Input data is 2X multiplexed, and the XCLK clock signal can be 1X or 2X times the pixel rate. The CH7303 can support a pixel rate of 165MHz. This operating mode uses all 8 bits of the DAC's 10-bit range, and provides a nominal signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75 doubly terminated load. No scaling, scan conversion or flicker filtering is applied in Bypass modes.
2.2
DVI Output
2.2.1 DVI Transmitter In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7303 from the graphics controller's digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the pixel rate. Some examples of modes supported are shown in the table. For the table below, clock frequencies for given modes were taken from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications. Any values of pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below 165MHz. The input format can be any RGB format or YCrCb (see Input Data Formats section). Table 9: DVI Output Graphics Active Aspect Resolution Ratio 720x400 640x400 640x480 720x480 720x576 800x600 1024x768 1280x720 4:3 8:5 4:3 4:3 4:3 4:3 4:3 16:9 Pixel Aspect Ratio 1.35:1.00 1:1 1:1 9:8 15:12 1:1 1:1 1:1 Refresh Rate (Hz) <85 <85 <85 59.94 50 <85 <85 <60 XCLK Frequency (MHz) <35.5 <31.5 <36 27 27 <57 <95 <67 DVI Frequency (MHz) <355 <315 <360 270 270 <570 <950 <670
2.3
Input Interface
2.3.1 Overview Two distinct methods of transferring data to the CH7303 are described. They are: * Multiplexed data, clock input at 1X the pixel rate * Multiplexed data, clock input at 2X the pixel rate For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7303 is latched with both edges of the clock (also referred to as dual edge transfer mode or DDR). For the multiplexed data, clock at 2X pixel rate the data applied to the CH7303 is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is programmable. In dual edge transfer modes, the clock edge used to latch the first half of each pixel is programmable. 6 209-0000-031 Rev. 0.4, 8/26/2002
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CH7303
2.3.2 Interface Voltage Levels The graphics controller interface can operate at a variable voltage level controlled by the voltage on the VDDV pin. This should be set to the maximum voltage of the interface (typically 3.3V or adjustable between 1.1 and 1.8V). The VREF pin is the voltage reference for the data, date enable, clock and sync inputs and must be tied to VDDV/2. This is typically done using a resistor divider. 2.3.3 Input Clock and Data Timing Diagram Figure 3 below shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform represents the input clock for single edge transfer (SDR) methods. The second XCLK/XCLK* waveform represents the input clock for the dual edge transfer (DDR) method. The timing requirements are given in section Error! Reference source not found..
XCLK/ XCLK* XCLK/ XCLK* D[11:0]
H
V
Figure 3: Clock, Data and Interface Timing 2.3.4 Data De-skew Feature The de-skew feature allows adjustment of the input setup and hold time. The input data D[14:0] can be latched slightly before or after the latching edge of XCLK depending on the amount of the de-skew. Note that the XCLK is not changed, only the time at which the data is latch relative to XCLK. .The de-skew is controlled using the XCMD[3:0] bits located in CH7303 register. The delay tCD between clock and data is given by the following formula: tCD = - XCMD[3:0] * tSTEP for 0 XCMD[3:0] 7 tCD = (XCMD[3:0] - 8) * tSTEP for 8 XCMD[3:0] 15 where XCMD is a number between 0 and 15 represented as a binary code tSTEP is the adjustment increment
2.3.5 Input Data Formats The CH7303 supports 9 different multiplexed data formats, each of which can be used with a 1X clock latching data on both clock edges, or a 2X clock latching data with a single edge (rising or falling depending on the value of the MCP bit - rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal). The input data formats are (IDF[2:0]): IDF 0 1 2 3 4 5 6 7 8 209-0000-031 Description 12-bit multiplexed RGB input (24-bit color), (multiplex scheme 1) 12-bit multiplexed RGB input (24-bit color), (multiplex scheme 2) 8-bit multiplexed RGB input (16-bit color, 565) 8-bit multiplexed RGB input (15-bit color, 555) 8-bit multiplexed YCrCb input (24-bit color), (Y, Cr and Cb are multiplexed) 12-bit multiplexed RGB input (24-bit color), (multiplex scheme A3 - edge-pair) 15-bit multiplexed RGB input (30-bit color), (multiplex scheme B1 - half-half mode) 15-bit multiplexed RGB input (30-bit color), (multiplex scheme B2 - half-color mode) 15-bit multiplexed RGB input (30-bit color), (multiplex scheme B3 - edge pair mode) Rev. 0.4, 8/26/2002 7
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CH7303
The input data format is shown in Figure 4 below. The Pixel Data bus represents a 15-bit, 12-bit or 8-bit multiplexed data stream, which contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate, and each pair of Pn values (e.g.; P0a and P0b) will contain a complete pixel encoded as shown in Table 9 through Table 8. It is assumed that the first clock cycle following the leading edge of the incoming horizontal sync signal contains the first word (Pxa) of a pixel, if an active pixel was present immediately following the horizontal sync. This does not mean that active data should immediately follow the horizontal sync, however. When the input is a YCrCb data stream the colordifference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples and the following Y1 byte refers to the next luminance sample, per ITU-R BT.656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in ITU-R BT.656). All non-active pixels should be 0 in RGB formats, and 16 for Y, 128 for Cr and Cb in YCrCb formats.
Hx XCLKx
(2X)
SAV
XCLKx
(1X)
DEx
Dx[11:0]
P0a
P0b
P1a
P1b
P2a
P2b
Figure 4: 12-bit Multiplexed Input Data Formats (IDFx = 0,1,2,3,4) Table 5: Multiplexed Input Data Formats (IDF = 0, 1) IDF = 0 Format = 12-bit RGB Pixel # P0a P0b P1a Bus Data D[11] G0[3] R0[7] G1[3] D[10] G0[2] R0[6] G1[2] D[9] G0[1] R0[5] G1[1] D[8] G0[0] R0[4] G1[0] D[7] B0[7] R0[3] B1[7] D[6] B0[6] R0[2] B1[6] D[5] B0[5] R0[1] B1[5] D[4] B0[4] R0[0] B1[4] D[3] B0[3] G0[7] B1[3] D[2] B0[2] G0[6] B1[2] D[1] B0[1] G0[5] B1[1] D[0] B0[0] G0[4] B1[0] Table 6: Multiplexed Input Data Formats (IDF = 2, 3) IDF = 2 Format = RGB 5-6-5 Pixel # P0a P0b P1a Bus Data D[11] G0[4] R0[7] G1[4] D[10] G0[3] R0[6] G1[3] D[9] G0[2] R0[5] G1[2] D[8] B0[7] R0[4] B1[7] D[7] B0[6] R0[3] B1[6] D[6] B0[5] G0[7] B1[5] D[5] B0[4] G0[6] B1[4] D[4] B0[3] G0[5] B1[3] 8 1 12-bit RGB P0b P1a R0[7] G1[4] R0[6] G1[3] R0[5] G1[2] R0[4] B1[7] R0[3] B1[6] G0[7] B1[5] G0[6] B1[4] G0[5] B1[3] R0[2] G1[0] R0[1] B1[2] R0[0] B1[1] G0[1] B1[0]
P1b R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4]
P0a G0[4] G0[3] G0[2] B0[7] B0[6] B0[5] B0[4] B0[3] G0[0] B0[2] B0[1] B0[0]
P1b R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6] G1[5] R1[2] R1[1] R1[0] G1[1]
P1b R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6] G1[5]
P0a G0[5] G0[4] G0[3] B0[7] B0[6] B0[5] B0[4] B0[3]
3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] 209-0000-031 Rev. 0.4, 8/26/2002
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Table 7: Multiplexed Input Data Formats (IDF = 4) IDF = Format = Pixel # P0a P0b P1a Bus Data D[7] Cb0[7] Y0[7] Cr0[7] D[6] Cb0[6] Y0[6] Cr0[6] D[5] Cb0[5] Y0[5] Cr0[5] D[4] Cb0[4] Y0[4] Cr0[4] D[3] Cb0[3] Y0[3] Cr0[3] D[2] Cb0[2] Y0[2] Cr0[2] D[1] Cb0[1] Y0[1] Cr0[1] D[0] Cb0[0] Y0[0] Cr0[0] 4 YCrCb 8-bit P1b P2a Y1[7] Cb2[7] Y1[6] Cb2[6] Y1[5] Cb2[5] Y1[4] Cb2[4] Y1[3] Cb2[3] Y1[2] Cb2[2] Y1[1] Cb2[1] Y1[0] Cb2[0]
CH7303
P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0]
P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0]
P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
Table 8: Embedded Sync in Multiplexed Data Format (IDF=4) IDF = 4 Format = YCrCb 8-bit Pixel # P0a P0b P1a P1b P2a Bus Data D[7] 1 0 0 S[7] Cb2[7] D[6] 1 0 0 S[6] Cb2[6] D[5] 1 0 0 S[5] Cb2[5] D[4] 1 0 0 S[4] Cb2[4] D[3] 1 0 0 S[3] Cb2[3] D[2] 1 0 0 S[2] Cb2[2] D[1] 1 0 0 S[1] Cb2[1] D[0] 1 0 0 S[0] Cb2[0]
P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0]
P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0]
P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
In this mode, the S[7:0] byte contains the following data: S[6] = F = 1 during field 2, 0 during field 1 S[5] = V = 1 during field (frame) blank, 0 elsewhere S[4] = H = 1 during EAV (synchronization reference at the end of active video) 0 during SAV (synchronization reference at the start of active video) Bits S[7] and S[3:0] are ignored. Table 9: Multiplexed Input Data Formats (IDF = 6, 7, 8) IDF = 6 7 Format = 15-bit RGB 15-bit RGB Pixel # P0a P0b P0a P0b Bus Data D[14] G0[4] R0[9] R0[4] R0[9] D[13] G0[3] R0[8] R0[3] R0[8] D[12] G0[2] R0[7] R0[2] R0[7] Bus Data D[11] G0[1] R0[6] R0[1] R0[6] D[10] G0[0] R0[5] R0[0] R0[5] D[9] B0[9] R0[4] G0[4] G0[9] D[8] B0[8] R0[3] G0[3] G0[8] D[7] B0[7] R0[2] G0[2] G0[7] D[6] B0[6] R0[1] G0[1] G0[6] D[5] B0[5] R0[0] G0[0] G0[5] D[4] B0[4] G0[9] B0[4] B0[9] D[3] B0[3] G0[8] B0[3] B0[8] D[2] B0[2] G0[7] B0[2] B0[7] D[1] B0[1] G0[6] B0[1] B0[6] D[0] B0[0] G0[5] B0[0] B0[5] 8 15-bit RGB P0b R0[9] R0[7] R0[5] R0[3] R0[1] G0[9] G0[7] G0[5] G0[3] G0[1] B0[9] B0[7] B0[5] B0[3] B0[1]
P0a R0[8] R0[6] R0[4] R0[2] R0[0] G0[8] G0[6] G0[4] G0[2] G0[0] B0[8] B0[6] B0[4] B0[2] B0[0]
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CHRONTEL
3.0 Electrical Specifications
3.1 Absolute Maximum Ratings
Description
All power supplies relative to GND Input voltage of all digital pins TSC TAMB TSTOR TJ TVPS Analog output short circuit duration Ambient operating temperature Storage temperature Junction temperature Vapor phase soldering (1 minute) 0 -65
CH7303
Symbol
Min
-0.5 GND - 0.5
Typ
Max
5.0 VDD + 0.5
Units
V V Sec
Indefinite 85 150 150 220
C C C C
Note: 1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than 0.5V can induce destructive latchup.
3.2
Recommended Operating Conditions
Description
PLL Power Supply Voltage DAC Power Supply Voltage Digital Power Supply Voltage I/O Power Supply Voltage Output load to DAC Outputs
Symbol
AVDD VDD DVDD VDDV RL
Min
3.1 3.1 3.1 1.1
Typ
3.3 3.3 3.3 1.8 37.5
Max
3.6 3.6 3.6 3.6
Units
V V V V
10
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Rev. 0.4,
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CHRONTEL
3.3
(Operating Conditions: TA = 0C - 70C, VDD =3.3V 5%) Symbol Description
Video D/A Resolution Full scale output current Video level error IVDD IVDDV IPD Total supply current VDDV (1.8V) current (15pF load) Total Power Down Current TBD 4 0.06
CH7303
Electrical Characteristics
Min
10
Typ
10 33.9
Max
10
Units
bits mA
10
% mA mA mA
3.4
DC Specifications
Symbol Description SPD (serial port data) Output Low Voltage Serial Port (SPC, SPD) Input High Voltage Serial Port (SPC, SPD) Input Low Voltage Hysteresis of Inputs D[0-14] Input High Voltage D[0-14] Input Low Voltage GPIOx, RESET*, AS, HPDET Input High Voltage GPIOx, RESET*, AS, HPDET Input Low Voltage Pull Up Current (GPIO, RESET*, AS) DVDD=3.3V Test Condition IOL = 2.0 mA Min Typ Max 0.4 Unit V
VSDOL VSPIH VSPIL VHYS VDATAIH VDATAIL VMISCIH VMISCIL IMISCPU IMISCPD VMISCOH VMISCOL VH VL VSWING VOFF
1.0
VDD + 0.5
V
GND-0.5
0.4
V
0.25 Vref+0.25 GND-0.5 2.7 DVDD+0.5 Vref-0.25 VDD + 0.5
V V V V
DVDD=3.3V
GND-0.5
0.6
V
VIN = 0V
0.5
5.0
uA
Pull Down Current (HPDET) GPIOx, VSYNC, HSYNC Output High Voltage GPIOx, VSYNC, HSYNC Output Low Voltage DVI Single Ended Output High Voltage DVI Single Ended Output Low Voltage DVI Single Ended Output Swing Voltage DVI Single Ended Standby Output Voltage
VIN = 3.3V
0.5
5.0
uA
IOH = -0.4mA
DVDD-0.2
V
IOL = 3.2mA TVDD = 3.3V 5% RTERM = 50 1% RSWING = 2400 1%
0.2
V
TVDD - 0.01 TVDD - 0.6 400 TVDD - 0.01
TVDD + 0.01 TVDD - 0.4 600 TVDD + 0.01
V
V
mVp-p V
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CHRONTEL
Note : HPDET inputs and GPIOx, VSYNC and HSYNC outputs.
CH7303
VDATA - refers to all digital data (D[14:0]), clock (XCLK, XCLK*), sync (H, V) and DE inputs. VMISC - refers to GPIOx, RESET*, AS and
3.5
AC Specifications
Symbol Description Input (XCLK) frequency Pixel time period Input (XCLK) Duty Cycle XCLK clock jitter tolerance DVI Output Rise Time (20% - 80%) TS + TH < 1.2ns fXCLK = 75MHz fXCLK = 165MHz 75 Test Condition Min 25 6.06 30 2 242 Typ Max 165 40 70 Unit MHz ns % ns ps
fXCLK tPIXEL DCXCLK tXJIT tDVIR tDVIF tSKDIFF tSKCC tDVIJIT TS
DVI Output Fall Time (20% - 80%) DVI Output intra-pair skew DVI Output inter-pair skew DVI Output Clock Jitter Setup Time: D[11:0], H, V and DE to XCLK, XCLK*
fXCLK = 165MHz
75
242
ps
fXCLK = 165MHz fXCLK = 165MHz fXCLK = 165MHz XCLK = XCLK* to D[11:0], H, V, DE = Vref TBD
90 1.2 150
ps ns ps ns
TH
Hold Time: D[11:0], H, V and DE to XCLK, XCLK*
D[11:0], H, V, DE = Vref to XCLK = XCLK*
TBD
ns
tSTEP
De-skew time increment
50
80
ps
12
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Rev. 0.4,
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CHRONTEL
3.6
3.6.1
CH7303
Timing Information
Clock - Slave, Sync - Slave Mode
t2
XCLK
V IH V IL
XCLK* D[11:0]
V IH V IL tS V IH P0a V IL tS tH P0b P1a P1b P2a P2b t3 tH
DE
V IH V IL tS
H V
V IH V IL V IH V IL t3 64 PIXELS
1 VGA Line t3
Figure 5: Timing for Clock - Slave, Sync - Slave Mode Table 10: Timing for Clock - Slave, Sync - Slave Mode
Symbol t2 t3 Parameter XCLK & XCLK* rise/fall time w/15pF load D[11:0], H, V & DE rise/fall time w/ 15pF load Min Typ 3 3 Max Unit ns ns
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8/26/2002
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CHRONTEL
4.0 Package Dimensions
A B I
CH7303
1
A
B
H
C
D
J
F G
LEAD CO-PLANARITY
E
.004 "
Table of Dimensions No. of Leads 64 (10 X 10 mm) MilliMIN meters MAX
A 12
B 10
C 0.50
D 0.17 0.27
SYMBOL E F 1.35 0.05 1.45 0.15
G 1.00
H 0.45 0.75
I 0.09 0.20
J 0 7
Figure 6: 64 Pin LQFP Package
14
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CHRONTEL
Disclaimer
CH7303
This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
Chrontel
2210 O'Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com
2002 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A.
209-0000-031
Rev. 0.4,
8/26/2002
15

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